Encore’s H.264 encoder is optimized for various ARM and DSP architectures by making optimal use of advanced multimedia architectural features, efficient use of system cache, DMA engine etc.

Features

• H.264 Baseline Profile up-to level 3.0 supported.
• Encoding of Progressive frame pictures.
• Multiple reference frames.
• Sub pixel motion estimation.
• Supports all sub partitions (16x16 to 4x4).
• Configurable search range and unrestricted motion vector search in motion estimation.
• Configurable multiple slices per picture.
• Configurable IDR frame insertion.
• Intra macro block insertion in inter frames.
• Configurable quantization parameter selection.
• Bit Rate control.
• Configurable deblocking filter support.
• Error resilience features such as adaptive intra refresh, Constrained intra prediction, FMO support.
• Configurable GOP length.
• Arbitrary Picture resolutions up to D1.
• Speed and quality balance (High speed, high quality, normal mode).
• Flexible user configurable options to operate encoder for different kind of applications.
• Flexible interface for easy integration.

Platforms

• Texas Instrument (TI’s) C64x (TMS320C64x), C64x+/DaVinci, OMAP2/OMAP-2430, OMAP3 devices.
• ARM v7 architecture (Cortex-A8 NEON technology based Cortex A series) based platforms (OMAP 3503).

Test and Validation

• Various test sequences have been passed through H.264 encoder and PSNR, bit rate values are measured with different encoder configurations.
• The bit streams generated by Encoder have been passed through JM reference decoder for validation.

Performance Statistics

The H.264 video encoder (MCPS and Memory) performance numbers are provided in this section:

MCPS Statistics (64x+)

• MCPS are based on average number of cycles per frame computed for all resolutions @ 30 fps.
• Program memory, I/O buffers, stack in external memory with the memory/cache configuration shown below
• L1P – 32KB Program cache
• L1D – 16KB Data cache and 64KB data memory
• L2 – 64KB cache
• MCPS numbers may differ based on the memory placement of code and data (I-Cache, D-Cache and external memory) and also the bit rate and quality requirement and encoder configuration parameters.
• The algorithm uses TI’s DMAN3 library for logical allocation of DMA channels.
• Higher resolutions can be supported based on the availability of target memory and CPU power.

Memory Statistics

• All Numbers are in KBytes.
• Input and output buffers are not included in the data memory usage.
• Memory requirement increases as the configured number of reference frame count increases.

MCPS Statistics (Cortex-A8)

• MCPS are measured on real OMAP-3503 based hardware running Linux.
• Avg. MCPS is based on average number of cycles per frame @ 30 fps
• Measured with program memory, data memory, I/O buffers, stack in external memory with the memory/cache configuration shown below:
• L1P – 16 KB
• L1D – 16 KB
• L2 – 256 KB
• MCPS numbers may differ based on the memory placement, cache configuration and also encoder configuration

For evaluation or further information please contact ip@ncoretech.com